VLSI Design

    Combinational Loops When the output of a combination logic is fed back to one of its input, a combination loop is formed. ATPG tool simulates the design assuming zero delay in combinational elements which may result in undetermined output for one or more input combinations. (Output of final OR gate is unknown this value fedback to input create wrong controllability ) Figure 11: Combinational Loops As shown above, the input combination (A, B, C) = (1, 0, 0) will create oscillations in the circuit. To prevent this, the tool breaks the loop and models it as a TIEX block in the feedback path ( complete path will disconnect b/w 2 flops )which results in coverage loss. Therefore such loops should be avoided. This loops EDA tool will break automatically at random points and in that case some paths won’t be timed.so it’s better to redesign RTL instead of missing few critical timing paths . Combination loop : a)  else command missed in if loop . b) LHS variable is defined...

 Worst cold : more timing violations that worst case hot (temperature inversion) Physical aware DMSA : no voltage area information ( we are proving def , lef (std cell pin info ) and tf (routing info ) . So difficult to provide eco as mv violation need to take care by designers .  And ICC specific command to fix mv violations .

 Graph based path analysis : Tool consider worst input slew for setup and best input slew for hold analysis ( worst delay for setup and best delay for hold ) . Run time is less and pessimistic analysis . Path based analysis : actual input slew is used ,so delay value will be accurate . Longer runtime .

 With the help of PT (sign off STA tools ) Make use of positive slack and recover leakage power by swapping cells with higher VT (same footprint ).

 Endpoint hold fixing : more number of buffer addition , Less TAT, more predictable or sure shot fix. DMSA hold fixing : Optimal number of buffer , Common point buffer insertion .

 To remove pessimistic value to become more realistic. pt_shell>  set_operating_conditions -analysis_type \                o n_chip_variation -min MIN -max MAX pt_shell>  set_timing_derate -net -min 0.78 -max 1.00 For setup time analysis clock launch path is 100% worst case max path analysis and capture path is 78% min path analysis . During setup analysis U1 will have 2 different delay values (common path for max and min (launch / capture analysis ). To remove this pessimism launch path extra added delay get removed in capture path to get more realistic value .(because for setup analysis capture clock path is always min so it can’t be max path and extra added value in data path launch clock max analysis should be removed ) the setup check considers that cell U1 simultaneously has two different delays,  min= 0.64 and max= 0.80 resulting in a pessimistic analysis delays in the amount of 0.16.