Combinations timing loop

Combinational Loops

When the output of a combination logic is fed back to one of its input, a combination loop is formed. ATPG tool simulates the design assuming zero delay in combinational elements which may result in undetermined output for one or more input combinations. (Output of final OR gate is unknown this value fedback to input create wrong controllability )

Figure 11: Combinational Loops

As shown above, the input combination (A, B, C) = (1, 0, 0) will create oscillations in the circuit. To prevent this, the tool breaks the loop and models it as a TIEX block in the feedback path ( complete path will disconnect b/w 2 flops )which results in coverage loss. Therefore such loops should be avoided.

This loops EDA tool will break automatically at random points and in that case some paths won’t be timed.so it’s better to redesign RTL instead of missing few critical timing paths .

Combination loop : a) else command missed in if loop . b) LHS variable is defined in RHS example always_comb = a =b ? c:a

http://vlsi-soc.blogspot.com/2013/05/combinational-loops.html?m=1

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