Timing ECOs : How timing engineers should fix last mile timing problems

First target in below order ,

DRC/DRV fixes :

1) Target clock DRV/DRCs first (This will change setup or hold windows (which in turn change data path ) as this is tabulated based on clock trans and data trans ).

Max Tran / Max cap , fixing one would fix the other one . Also if we keep these values in library limit/higher side , this might result in increased power dissipation. ( Max clock Tran is usually 10% of clock period and is defined by designers )

Usually max trans / max cap limit is set either by timing libraries or some tighter values explicitly defined by designers. Usually the library limit will be quite higher than what set by designers . Any extrapolation outside the lookup table value will results in pessimistic delay value (load out of slope errors ).

Trans/ Cap can be fixed by load splitting , upsizing driver or buffering long net

2) Target data DRVs (Usually 20% of clock groups , but for slow clock like DFT/TEST this may create load out of slope in that case we will go with library limit .)

Comments

GBA vs PBA

Graph based path analysis : Tool consider worst input slew for setup and best input slew for hold analysis ( worst delay for setup and best delay for hold ) . Run time is less and pessimistic analysis . Path based analysis : actual input slew is used ,so delay value will be accurate . Longer runtime .

Physical cells used in IC design

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MCMM

Multi-mode multi-corner (MMMC) analysis refers to performing STA across multiple operating modes , PVT corners and parasitic interconnect corners (rcworst , cworst etc ) at the same time. MCMM file is To analyse the design over various modes and corners . VLSI design can be modeled in either functional or test mode etc Each mode at varied process corners. We need to ensure that the design is stable across all corners (PVT corners ). Mode : A mode is defined by a set of clocks, timing constraints, Supply voltage and libraries. Many chip have multiple modes such as functional modes, test mode, sleep mode, etc Corner: A corner is defined as a set of libraries characterized for process, voltage, and temperature variations (cell line) and interconnect corner .Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment i...

VLSI Design

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