VLSI Design

 Why endcap cells are used in design ? There are high chances to get damaged the gate of standard cells placed at the boundary during the manufacturing of chip. Nwell terminates within endcap cells , so we cannot replace filler with endcap as filler is for nwell continuity , also dummy poly layers present in endcap cells protect from wave proximity effect. Tap cells differ in such a way that nwell continuous and not continuous in endcap cells . To avoid the base layer DRC (Nwell and Implant layer) at the boundary. To make the proper alignment with the other block. The end cap cell or boundary cell is placed at both the ends of each placement row to terminate the row.  It has also been placed at the top and bottom row at the block level to make integration with other blocks End caps are added before std cells placement and are preplaced fixed cells which added immediately after site row creation. Boundary cells have mainly Nwell layer, implant layers, and dummy poly layer and m...

 First target in below order , DRC/DRV fixes :  1) Target clock DRV/DRCs first (This will change setup or hold windows (which in turn change data path ) as this is tabulated based on clock trans and data trans ). Max Tran / Max cap , fixing one would fix the other one . Also if we keep these values in library limit/higher side , this might result in increased power dissipation. ( Max clock Tran is usually 10% of clock period and is defined by designers ) Usually max trans / max cap limit is set either by timing libraries or some tighter values explicitly defined by designers. Usually the library limit will be quite higher than what set by designers . Any extrapolation outside the lookup table value will results in pessimistic delay value (load out of slope errors ). Trans/ Cap can be fixed by load splitting , upsizing driver or buffering  long net  2) Target data DRVs (Usually 20% of clock groups , but for slow clock like DFT/TEST this may create load out of slope in...

Both at a time is not possible then there won’t be any window for data validity . If setup time is negative, then the absolute latest that the data can become valid is actually after the active clock edge, Obviously the hold time  must  be positive  and of greater magnitude  or there would be no window for data validity.  If the hold time is negative, then the absolute earliest the data no longer needs to be valid is before the active clock edge, so it can change just before the clock edge and the previous value will be correctly recognized. Obviously, the setup time must be positive and of   greater   magnitude or there would be no window. . For a FF,  (Setup time + hold time) will always be greater than or equal to zero! Hold time on the other hand depends on the actual skew inside the flip flop between the two complementary clocks that the transmission gates receive. It is the (delay of transmission gate - the skew). Now, if the skew is more th...

Multi-mode multi-corner (MMMC) analysis refers to performing STA across  multiple operating modes ,  PVT corners  and  parasitic interconnect corners  (rcworst , cworst etc ) at the same time. MCMM file is To analyse the design over various modes and corners .   VLSI design can be modeled in either functional or test mode etc Each mode at varied process corners. We need to ensure that the design is stable across all corners (PVT corners ). Mode : A mode is defined by a set of clocks, timing constraints, Supply voltage and libraries. Many chip have multiple modes such as functional modes, test mode, sleep mode, etc Corner: A corner is defined as a set of libraries characterized for process, voltage, and temperature variations (cell line) and interconnect corner .Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment i...